module tx_sys (/*AUTOARG*/
   // Outputs
   int_data_in0, in_valid0, int_data_in1, in_valid1, float_data_a0,
   float_data_a1, float_data_m0, float_data_m1, float_data_avld,
   float_data_mvld,
   // Inputs
   clk, rst_n
   );

input  clk   ;
input  rst_n ;

output  [31:0]  int_data_in0 ;
output          in_valid0    ; 

output  [31:0]  int_data_in1 ;
output          in_valid1    ; 

output  [31:0]   float_data_a0 ;
output  [31:0]   float_data_a1 ;
output  [31:0]   float_data_m0 ;
output  [31:0]   float_data_m1 ;

output     float_data_avld ;
output     float_data_mvld ;

///////////////////////////////////////////////
reg     [31:0]  int_data_in0 ;
reg             in_valid0    ; 
reg     [31:0]  int_data_in1 ;
reg             in_valid1    ; 

reg    [31:0]   float_data_a0 ;
reg    [31:0]   float_data_a1 ;
reg    [31:0]   float_data_m0 ;
reg    [31:0]   float_data_m1 ;


reg        float_data_avld ;
reg        float_data_mvld ;

reg      [31:0]   cnt  ;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n) begin 
		cnt <= 'd0;
	end
	else begin 
		cnt <= cnt+1;
	end
end



//always@(posedge clk or negedge rst_n)
//begin
//	if(~rst_n) begin 
//		in_valid0 <= 'd0;
//		int_data_in0 <= 'd0 ;
//		in_valid1 <= 'd0;
//		int_data_in1 <= 'd0 ;
//	end
//	else if ( |cnt   && (cnt<='d2048)  ) begin 
//		in_valid0 <= 'd1;
//		int_data_in0 <= cnt ;
//		in_valid1 <= 'd1;
//		int_data_in1 <= cnt ;
//	end
//
//       else if (  cnt<='d4096  ) begin 
//		in_valid0 <= 'd0;
//		in_valid1 <= 'd0;
//       end
//
//      	else if ( |cnt   && (cnt<='d8192)  ) begin 
//		in_valid0 <= 'd1;
//		int_data_in0 <= -(cnt-4096) ;
//		in_valid1 <= 'd1;
//		int_data_in1 <= -(cnt-4096) ;
//	end
//
//
//	else begin 
//		in_valid0 <= 'd0;
//		int_data_in0 <= 'd0 ;
//		in_valid1 <= 'd0;
//		int_data_in1 <= 'd0 ;
//	end
//end



integer fp_input;
integer fp_a0_input;
integer fp_a1_input;
integer fp_m0_input;
integer fp_m1_input;

integer result_fp;
integer result_a0_fp;
integer result_a1_fp;
integer result_m0_fp;
integer result_m1_fp;

reg   [31:0]      float_in;
reg   [31:0]      float_a0_in;
reg   [31:0]      float_a1_in;
reg   [31:0]      float_m0_in;
reg   [31:0]      float_m1_in;
initial begin
  fp_input = $fopen("float.txt","r");
  result_fp =$fscanf(fp_input , "%d"  , float_in );

  fp_a0_input  = $fopen("float_bina.txt","r");
  result_a0_fp = $fscanf(fp_a0_input , "%b"  , float_a0_in );
  fp_a1_input  = $fopen("float_binb.txt","r");
  result_a1_fp = $fscanf(fp_a1_input , "%b"  , float_a1_in );

  fp_m0_input  = $fopen("float_binma.txt","r");
  result_m0_fp = $fscanf(fp_m0_input , "%b"  , float_m0_in );
  fp_m1_input  = $fopen("float_binmb.txt","r");
  result_m1_fp = $fscanf(fp_m1_input , "%b"  , float_m1_in );

 // $fscanf(fp_a0_input , "%b"  , float_a0_in );
 // $fscanf(fp_a1_input , "%b"  , float_a1_in );

  
end



always@(posedge clk or negedge rst_n)
begin
	if(~rst_n) begin 
		in_valid0 <= 'd0;
		int_data_in0 <= 'd0 ;
		in_valid1 <= 'd0;
		int_data_in1 <= 'd0 ;
	end
	else if (  cnt<=`LEN   ) begin 
		in_valid0 <= 'd1;
		int_data_in0 <=  float_in ;
		in_valid1 <= 'd1;
		int_data_in1 <= float_in ;
  		result_fp =$fscanf(fp_input , "%d"  , float_in );
	end
      	else begin 
		in_valid0 <= 'd0;
		in_valid1 <= 'd0;
	end
end



//reg    [31:0]   float_data_a0 ;
//reg    [31:0]   float_data_a1 ;
//reg    [31:0]   float_data_m0 ;
//reg    [31:0]   float_data_m1 ;
//reg        float_data_avld ;
//reg        float_data_mvld ;
//


always@(posedge clk or negedge rst_n)
begin
	if(~rst_n) begin 
		float_data_avld <= 'd0;
		float_data_a0 <= 'd0 ;
		float_data_a1 <= 'd0 ;
	end
	else if (  cnt<=`LEN    ) begin 
		float_data_avld <= 'd1;
		float_data_a0 <=  float_a0_in ;
		float_data_a1 <=  float_a1_in ;

		//float_data_a0 <=  32'hbf29_eeb2 ;
		//float_data_a1 <=  32'h3f2b_67cf ;


  		result_a0_fp =$fscanf(fp_a0_input , "%b"  , float_a0_in );
  		result_a1_fp =$fscanf(fp_a1_input , "%b"  , float_a1_in );
	end
      	else begin 
		float_data_avld <= 'd0;
	end
end


always@(posedge clk or negedge rst_n)
begin
	if(~rst_n) begin 
		float_data_mvld <= 'd0;
		float_data_m0 <= 'd0 ;
		float_data_m1 <= 'd0 ;
	end
	else if (  cnt<=`LEN   ) begin 
		float_data_mvld <= 'd1;
		float_data_m0 <=  float_m0_in ;
		float_data_m1 <=  float_m1_in ;
  		result_m0_fp =$fscanf(fp_m0_input , "%b"  , float_m0_in );
  		result_m1_fp =$fscanf(fp_m1_input , "%b"  , float_m1_in );
	end
      	else begin 
		float_data_mvld <= 'd0;
	end
end


endmodule

